86 lines
2.9 KiB
C
86 lines
2.9 KiB
C
/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file bcm2837.h
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#ifndef BCM2837_H_13CD1DB9_AAD7_4F1C_8669_37DED77135D1
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#define BCM2837_H_13CD1DB9_AAD7_4F1C_8669_37DED77135D1
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#define PERIPHERAL_BASE 0x3F000000
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/* Reserve 4 MB for the Kernel and its stack */
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#define MEMORY_LOW (4 * 1024 * 1024)
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#define MEMORY_HIGH PERIPHERAL_BASE
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#define MEMORY_SIZE (MEMORY_HIGH - MEMORY_LOW)
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#define MEMORY_PAGE_SIZE (4 * 1024)
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#define MEMORY_PAGE_COUNT (MEMORY_SIZE / MEMORY_PAGE_SIZE)
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/* GPIO */
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#define GPFSEL1 (PERIPHERAL_BASE + 0x00200004)
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#define GPSET0 (PERIPHERAL_BASE + 0x0020001C)
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#define GPCLR0 (PERIPHERAL_BASE + 0x00200028)
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#define GPPUD (PERIPHERAL_BASE + 0x00200094)
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#define GPPUDCLK0 (PERIPHERAL_BASE + 0x00200098)
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/* UART MINI */
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#define AUX_ENABLES (PERIPHERAL_BASE + 0x00215004)
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#define AUX_MU_IO_REG (PERIPHERAL_BASE + 0x00215040)
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#define AUX_MU_IER_REG (PERIPHERAL_BASE + 0x00215044)
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#define AUX_MU_IIR_REG (PERIPHERAL_BASE + 0x00215048)
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#define AUX_MU_LCR_REG (PERIPHERAL_BASE + 0x0021504C)
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#define AUX_MU_MCR_REG (PERIPHERAL_BASE + 0x00215050)
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#define AUX_MU_LSR_REG (PERIPHERAL_BASE + 0x00215054)
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#define AUX_MU_MSR_REG (PERIPHERAL_BASE + 0x00215058)
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#define AUX_MU_SCRATCH (PERIPHERAL_BASE + 0x0021505C)
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#define AUX_MU_CNTL_REG (PERIPHERAL_BASE + 0x00215060)
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#define AUX_MU_STAT_REG (PERIPHERAL_BASE + 0x00215064)
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#define AUX_MU_BAUD_REG (PERIPHERAL_BASE + 0x00215068)
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/* IRQ */
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#define IRQ_BASIC_PENDING (PERIPHERAL_BASE + 0x0000B200)
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#define IRQ_PENDING_1 (PERIPHERAL_BASE + 0x0000B204)
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#define IRQ_PENDING_2 (PERIPHERAL_BASE + 0x0000B208)
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#define FIQ_CONTROL (PERIPHERAL_BASE + 0x0000B20C)
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#define ENABLE_IRQS_1 (PERIPHERAL_BASE + 0x0000B210)
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#define ENABLE_IRQS_2 (PERIPHERAL_BASE + 0x0000B214)
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#define ENABLE_BASIC_IRQS (PERIPHERAL_BASE + 0x0000B218)
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#define DISABLE_IRQS_1 (PERIPHERAL_BASE + 0x0000B21C)
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#define DISABLE_IRQS_2 (PERIPHERAL_BASE + 0x0000B220)
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#define DISABLE_BASIC_IRQS (PERIPHERAL_BASE + 0x0000B224)
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/* SYSTEM TIMER */
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#define SYSTEM_TIMER_IRQ_0 (1 << 0)
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#define SYSTEM_TIMER_IRQ_1 (1 << 1)
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#define SYSTEM_TIMER_IRQ_2 (1 << 2)
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#define SYSTEM_TIMER_IRQ_3 (1 << 3)
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/* TIMER */
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#define TIMER_CS (PERIPHERAL_BASE + 0x00003000)
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#define TIMER_CLO (PERIPHERAL_BASE + 0x00003004)
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#define TIMER_CHI (PERIPHERAL_BASE + 0x00003008)
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#define TIMER_C0 (PERIPHERAL_BASE + 0x0000300C)
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#define TIMER_C1 (PERIPHERAL_BASE + 0x00003010)
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#define TIMER_C2 (PERIPHERAL_BASE + 0x00003014)
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#define TIMER_C3 (PERIPHERAL_BASE + 0x00003018)
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#define TIMER_CS_M0 (1 << 0)
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#define TIMER_CS_M1 (1 << 1)
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#define TIMER_CS_M2 (1 << 2)
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#define TIMER_CS_M3 (1 << 3)
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#endif /* !BCM2837_H */
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