Add context switching and basic scheduler
This commit is contained in:
parent
a93f257f2e
commit
26f05b04d7
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@ -56,7 +56,7 @@ AArch64_memzero:
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/* Exceptions Vector Table
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* */
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.macro SAVE_REGISTERS
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sub sp, sp, 256
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sub sp, sp, 272
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stp x0, x1, [sp, 16 * 0]
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stp x2, x3, [sp, 16 * 1]
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stp x4, x5, [sp, 16 * 2]
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@ -102,7 +102,7 @@ AArch64_memzero:
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ldp x4, x5, [sp, 16 * 2]
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ldp x2, x3, [sp, 16 * 1]
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ldp x0, x1, [sp, 16 * 0]
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add sp, sp, 256
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add sp, sp, 272
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.endm
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.macro VECTOR_ENTRY GOTO_LABEL
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@ -122,6 +122,59 @@ AArch64_memzero:
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die:
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b die
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.globl AArch64_switchContext
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AArch64_switchContext:
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/* Save current task context */
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sub sp, sp, 272
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stp x0, x1, [sp, 16 * 0]
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stp x2, x3, [sp, 16 * 1]
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stp x4, x5, [sp, 16 * 2]
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stp x6, x7, [sp, 16 * 3]
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stp x8, x9, [sp, 16 * 4]
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stp x10, x11, [sp, 16 * 5]
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stp x12, x13, [sp, 16 * 6]
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stp x14, x15, [sp, 16 * 7]
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stp x16, x17, [sp, 16 * 8]
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stp x18, x19, [sp, 16 * 9]
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stp x20, x21, [sp, 16 * 10]
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stp x22, x23, [sp, 16 * 11]
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stp x24, x25, [sp, 16 * 12]
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stp x26, x27, [sp, 16 * 13]
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stp x28, x29, [sp, 16 * 14]
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mrs x23, NZCV
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mrs x3, DAIF
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orr x23, x23, x3
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mrs x3, CurrentEL
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orr x23, x23, x3
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stp x30, x30, [sp, 16 * 15]
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str x23, [sp, 16 * 16]
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mov x2, sp
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str x2, [x0]
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/* Restore next task context */
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ldr x2, [x1]
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mov sp, x2
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ldr x30, [sp, 16 * 15]
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ldp x28, x29, [sp, 16 * 14]
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ldp x26, x27, [sp, 16 * 13]
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ldp x24, x25, [sp, 16 * 12]
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ldp x22, x23, [sp, 16 * 11]
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ldp x20, x21, [sp, 16 * 10]
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ldp x18, x19, [sp, 16 * 9]
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ldp x16, x17, [sp, 16 * 8]
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ldp x14, x15, [sp, 16 * 7]
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ldp x12, x13, [sp, 16 * 6]
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ldp x10, x11, [sp, 16 * 5]
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ldp x8, x9, [sp, 16 * 4]
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ldp x6, x7, [sp, 16 * 3]
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ldp x4, x5, [sp, 16 * 2]
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ldp x2, x3, [sp, 16 * 1]
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ldp x0, x1, [sp, 16 * 0]
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add sp, sp, 272
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ret
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.align 11
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.globl AArch64_vectors
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AArch64_vectors:
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@ -43,4 +43,7 @@ AArch64_disableIRQ(void);
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extern void
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AArch64_memzero(void *addr, unsigned long size);
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extern void
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AArch64_switchContext(void *currentTask, void *nextTask);
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#endif /* !AARCH64_H */
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@ -10,6 +10,6 @@ SECTIONS
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bss_end = .;
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. = ALIGN(8);
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. = . + 0x8000;
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stack_ptr = . ;
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. = . + 0x4000;
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ld_stackPtr = . ;
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}
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@ -31,7 +31,7 @@ set_el:
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eret
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set_stack:
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ldr x30, =stack_ptr /* defined in aarch64.ld */
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ldr x30, =ld_stackPtr /* defined in aarch64.ld */
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mov sp, x30
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bl skip
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skip:
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@ -16,6 +16,110 @@
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#ifndef AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
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#define AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
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#define AARCH64_LOCAL_INT_ROUTING *((uint32_t *) 0x40000024)
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#define AARCH64_LOCAL_TIMER_STATCTL *((uint32_t *) 0x40000034)
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#define AARCH64_LOCAL_TIMER_RECLR *((uint32_t *) 0x40000038)
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/* Timers interrupt control registers
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* */
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#define AARCH64_CORE0_TIMER_IRQCTL *((uint32_t *) 0x40000040)
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#define AARCH64_CORE1_TIMER_IRQCTL *((uint32_t *) 0x40000044)
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#define AARCH64_CORE2_TIMER_IRQCTL *((uint32_t *) 0x40000048)
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#define AARCH64_CORE3_TIMER_IRQCTL *((uint32_t *) 0x4000004C)
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/* Timer interrupr routing
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* */
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#define AARCH64_TIMER0_IRQ 0x01
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#define AARCH64_TIMER1_IRQ 0x02
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#define AARCH64_TIMER2_IRQ 0x04
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#define AARCH64_TIMER3_IRQ 0x08
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#define AARCH64_TIMER0_FIQ 0x10
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#define AARCH64_TIMER1_FIQ 0x20
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#define AARCH64_TIMER2_FIQ 0x40
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#define AARCH64_TIMER3_FIQ 0x80
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/* Mailbox control registers
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* */
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#define AARCH64_CORE0_MBOX_IRQCTL *((uint32_t *) 0x40000050)
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#define AARCH64_CORE1_MBOX_IRQCTL *((uint32_t *) 0x40000054)
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#define AARCH64_CORE2_MBOX_IRQCTL *((uint32_t *) 0x40000058)
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#define AARCH64_CORE3_MBOX_IRQCTL *((uint32_t *) 0x4000005C)
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/* Mailbox interrupr routing
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* */
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#define AARCH64_MBOX0_IRQ 0x01
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#define AARCH64_MBOX1_IRQ 0x02
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#define AARCH64_MBOX2_IRQ 0x04
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#define AARCH64_MBOX3_IRQ 0x08
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#define AARCH64_MBOX0_FIQ 0x10
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#define AARCH64_MBOX1_FIQ 0x20
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#define AARCH64_MBOX2_FIQ 0x40
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#define AARCH64_MBOX3_FIQ 0x80
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/* Source registers for IRQ / FIQ
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* */
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#define AARCH64_CORE0_IRQSRC *((uint32_t *) 0x40000060)
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#define AARCH64_CORE1_IRQSRC *((uint32_t *) 0x40000064)
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#define AARCH64_CORE2_IRQSRC *((uint32_t *) 0x40000068)
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#define AARCH64_CORE3_IRQSRC *((uint32_t *) 0x4000006C)
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#define AARCH64_CORE0_FIQSRC *((uint32_t *) 0x40000070)
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#define AARCH64_CORE1_FIQSRC *((uint32_t *) 0x40000074)
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#define AARCH64_CORE2_FIQSRC *((uint32_t *) 0x40000078)
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#define AARCH64_CORE3_FIQSRC *((uint32_t *) 0x4000007C)
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/* Interrupt source bits
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* */
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#define AARCH64_TIMER0_INTSRC 0x0001
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#define AARCH64_TIMER1_INTSRC 0x0002
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#define AARCH64_TIMER2_INTSRC 0x0004
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#define AARCH64_TIMER3_INTSRC 0x0008
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#define AARCH64_MBOX0_INTSRC 0x0010
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#define AARCH64_MBOX1_INTSRC 0x0020
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#define AARCH64_MBOX2_INTSRC 0x0040
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#define AARCH64_MBOX3_INTSRC 0x0080
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#define AARCH64_GPU_INTSRC 0x0100
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#define AARCH64_PMU_INTSRC 0x0200
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/* Mailbox write-set registers (write only)
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* */
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#define AARCH64_CORE0_MBOX0_SETREG *((uint32_t *) 0x40000080)
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#define AARCH64_CORE0_MBOX1_SETREG *((uint32_t *) 0x40000084)
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#define AARCH64_CORE0_MBOX2_SETREG *((uint32_t *) 0x40000088)
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#define AARCH64_CORE0_MBOX3_SETREG *((uint32_t *) 0x4000008C)
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#define AARCH64_CORE1_MBOX0_SETREG *((uint32_t *) 0x40000090)
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#define AARCH64_CORE1_MBOX1_SETREG *((uint32_t *) 0x40000094)
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#define AARCH64_CORE1_MBOX2_SETREG *((uint32_t *) 0x40000098)
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#define AARCH64_CORE1_MBOX3_SETREG *((uint32_t *) 0x4000009C)
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#define AARCH64_CORE2_MBOX0_SETREG *((uint32_t *) 0x400000A0)
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#define AARCH64_CORE2_MBOX1_SETREG *((uint32_t *) 0x400000A4)
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#define AARCH64_CORE2_MBOX2_SETREG *((uint32_t *) 0x400000A8)
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#define AARCH64_CORE2_MBOX3_SETREG *((uint32_t *) 0x400000AC)
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#define AARCH64_CORE3_MBOX0_SETREG *((uint32_t *) 0x400000B0)
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#define AARCH64_CORE3_MBOX1_SETREG *((uint32_t *) 0x400000B4)
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#define AARCH64_CORE3_MBOX2_SETREG *((uint32_t *) 0x400000B8)
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#define AARCH64_CORE3_MBOX3_SETREG *((uint32_t *) 0x400000BC)
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/* Mailbox write-clear registers (Read & Write)
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* */
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#define AARCH64_CORE0_MBOX0_RDCLREG *((uint32_t *) 0x400000C0)
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#define AARCH64_CORE0_MBOX1_RDCLREG *((uint32_t *) 0x400000C4)
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#define AARCH64_CORE0_MBOX2_RDCLREG *((uint32_t *) 0x400000C8)
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#define AARCH64_CORE0_MBOX3_RDCLREG *((uint32_t *) 0x400000CC)
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#define AARCH64_CORE1_MBOX0_RDCLREG *((uint32_t *) 0x400000D0)
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#define AARCH64_CORE1_MBOX1_RDCLREG *((uint32_t *) 0x400000D4)
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#define AARCH64_CORE1_MBOX2_RDCLREG *((uint32_t *) 0x400000D8)
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#define AARCH64_CORE1_MBOX3_RDCLREG *((uint32_t *) 0x400000DC)
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#define AARCH64_CORE2_MBOX0_RDCLREG *((uint32_t *) 0x400000E0)
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#define AARCH64_CORE2_MBOX1_RDCLREG *((uint32_t *) 0x400000E4)
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#define AARCH64_CORE2_MBOX2_RDCLREG *((uint32_t *) 0x400000E8)
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#define AARCH64_CORE2_MBOX3_RDCLREG *((uint32_t *) 0x400000EC)
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#define AARCH64_CORE3_MBOX0_RDCLREG *((uint32_t *) 0x400000F0)
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#define AARCH64_CORE3_MBOX1_RDCLREG *((uint32_t *) 0x400000F4)
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#define AARCH64_CORE3_MBOX2_RDCLREG *((uint32_t *) 0x400000F8)
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#define AARCH64_CORE3_MBOX3_RDCLREG *((uint32_t *) 0x400000FC)
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/* Saved Program Status Register (SPSR)
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* Exception Level 3 (EL3)
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* See page 389 of AArch64-Reference-Manual
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@ -62,6 +62,7 @@
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#define DISABLE_IRQS_2 (PERIPHERAL_BASE + 0x0000B220)
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#define DISABLE_BASIC_IRQS (PERIPHERAL_BASE + 0x0000B224)
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#define LOCAL_TIMER_IRQ 0
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/* SYSTEM TIMER */
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#define SYSTEM_TIMER_IRQ_0 (1 << 0)
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#define SYSTEM_TIMER_IRQ_1 (1 << 1)
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@ -25,10 +25,45 @@ unsigned int m_current = 0;
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#define CONFIG_ARM_TIMER 1
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#endif
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#define TIMER_ENABLE ((1 << 31) | (1 << 29) | (1 << 28))
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#define TIMER_RELOAD 1
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/*
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* https://www.raspberrypi.org/forums/viewtopic.php?t=213393
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* The sequence on a real PI3 is
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* 1.) Route the local timer to a core register 0x40000024 (bits 0..2)
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* QA7_rev3.4.pdf page 18 ... say write 0 which is core 0
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*
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* 2.) Setup timer status control register 0x40000034 (all 32 bits)
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* QA7_rev3.4.pdf page 17 ... reload value 5000000 = like half sec, enable clock, enable interrupt
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* You can play with clock prescalers etc later.
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* 3.) Hit timer interrupt clear and reload register 0x40000038 (bits 30 & 31)
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* QA7_rev3.4.pdf page 18 ... write 1 to both bits which clears irq signal and loads value from above
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*
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* 4.) Setup timer interrupt control register 0x40000040 (all bits ... zero all but the one bit set)
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* QA7_rev3.4.pdf page 13 ... now this depends what mode Core0 leaves your bootstub in.
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* If you did no EL changes in stub the core0 will still be in Hyp mode if like me you dropped it to SVC mode it is Non Secure
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*
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* If Core0 enters in Hyp mode ... set nCNTHPIRQ_IRQ bit 1
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* If Core0 enters in Svc mode ... set nCNTPNSIRQ_IRQ bit 2
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*
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* 5.) Now you need to enable global interupts
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* asm(" cpsie i")
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* */
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void
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Timer_init(void)
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{
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#if CONFIG_ARM_TIMER == 1
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/* Route local timer to a core0 */
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AARCH64_LOCAL_INT_ROUTING &= ~0x03;
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/* Set up timer status control register */
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AARCH64_LOCAL_TIMER_STATCTL = TIMER_ENABLE | TIMER_RELOAD;
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/* clear interrupt flag and reload timer */
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AARCH64_LOCAL_TIMER_RECLR |= (1 << 31) | (1 << 30);
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/* Set timer interrupt control register */
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AARCH64_CORE0_TIMER_IRQCTL = (1 << 1); /* nCNTPNSIR1 - Non Secure*/
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#else
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m_current = aarch64_get32r(TIMER_CLO);
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m_current += m_interval;
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@ -39,15 +74,23 @@ Timer_init(void)
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void
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Timer_incFromISR(void)
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{
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m_current++; /*= m_interval;*/
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#if CONFIG_ARM_TIMER == 1
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/* clear interrupt flag and reload timer */
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AARCH64_LOCAL_TIMER_RECLR |= (1 << 31) | (1 << 30);
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#else
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m_current += m_interval;
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aarch64_set32r(TIMER_C1, m_current);
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aarch64_set32r(TIMER_CS, TIMER_CS_M1);
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#endif
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/*
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Log_putS("Timer: ");
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Log_putI(m_current, 10);
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Log_putS("\r\n");
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*/
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}
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uint32_t
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Timer_getTicks(void)
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{
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return m_current;
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}
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@ -16,10 +16,14 @@
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#ifndef TIMER_H_8D327261_47D6_4832_8DC5_31BF1614A21F
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#define TIMER_H_8D327261_47D6_4832_8DC5_31BF1614A21F
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void
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Timer_init(void);
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void
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Timer_incFromISR(void);
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uint32_t
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Timer_getTicks(void);
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#endif /* !TIMER_H */
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@ -39,26 +39,26 @@ static const char *m_types[] = {
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};
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static unsigned long
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static void *
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IRQ_onTimerInterrupt(void)
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{
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Timer_incFromISR();
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return Task_scheduleFromISR();
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}
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void
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IRQ_init()
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{
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AArch64_setReg32(ENABLE_IRQS_1, SYSTEM_TIMER_IRQ_1);
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}
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unsigned long
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void *
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IRQ_onInterrupt(void)
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{
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unsigned int irq = AArch64_getReg32(IRQ_PENDING_1);
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switch(irq) {
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case LOCAL_TIMER_IRQ:
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case SYSTEM_TIMER_IRQ_1:
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return IRQ_onTimerInterrupt();
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@ -21,7 +21,7 @@
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void
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IRQ_init(void);
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unsigned long
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void *
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IRQ_onInterrupt(void);
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void
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@ -14,29 +14,46 @@
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*/
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#include <leos/log.h>
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#include <leos/arch.h>
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#include <leos/irq.h>
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#include <leos/leos.h>
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#include <leos/task.h>
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#include <drivers/timer/timer.h>
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void
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Leos_run(void)
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{
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Log_init();
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Log_putS("Starting Lowe OS (EL");
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Log_putS("Starting LEOS (EL");
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Log_putI(AArch64_getEL(), 10);
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Log_putS(")\r\n");
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AArch64_init();
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Timer_init();
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IRQ_init();
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Timer_init();
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IRQ_enable();
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Task_initSheduler();
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Task_create(Leos_demoTask, "Task 1");
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for (;;) {
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__asm__("WFE");
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Log_putU(Timer_getTicks(), 10);
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Log_putS(". idle\r\n");
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Task_yield();
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}
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}
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void
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Leos_demoTask(void *arg)
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{
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for (;;) {
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Log_putU(Timer_getTicks(), 10);
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Log_putS((const char *)arg);
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Log_putS("\r\n");
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Task_yield();
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}
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}
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@ -13,11 +13,166 @@
|
|||
* @see https://lowenware.com/
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <aarch64/aarch64.h>
|
||||
#include <drivers/soc/bcm2837/bcm2837.h>
|
||||
#include "memory.h"
|
||||
#include "task.h"
|
||||
|
||||
#define TASK_STATE_RUNNING 0
|
||||
|
||||
unsigned long
|
||||
Task_scheduleFromISR(void)
|
||||
#ifndef CONFIG_IDLE_TASK_STACK_SIZE
|
||||
#define CONFIG_IDLE_TASK_STACK_SIZE 0x4000
|
||||
#endif
|
||||
|
||||
struct Task {
|
||||
void *sp;
|
||||
void *stackStart;
|
||||
uint32_t stackSize;
|
||||
uint32_t lock;
|
||||
uint32_t counter;
|
||||
uint32_t cycles;
|
||||
int32_t priority;
|
||||
uint32_t state;
|
||||
char name[CONFIG_TASK_MAX_NAME_LEN + 1];
|
||||
struct Task *next;
|
||||
};
|
||||
|
||||
static struct Task *m_currentTask = NULL
|
||||
, *m_lastTask = NULL
|
||||
, m_idleTask = {
|
||||
.sp = NULL
|
||||
, .stackStart = NULL
|
||||
, .stackSize = CONFIG_IDLE_TASK_STACK_SIZE
|
||||
, .lock = 1
|
||||
, .counter = 1
|
||||
, .cycles = 1
|
||||
, .priority = 0
|
||||
, .state = TASK_STATE_RUNNING
|
||||
, .name = {'I', 'D', 'L', 'E', 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
|
||||
, .next = NULL
|
||||
};
|
||||
|
||||
static struct Task *
|
||||
scheduleNext(void)
|
||||
{
|
||||
struct Task *i, *next = NULL;
|
||||
int32_t priority = -1;
|
||||
|
||||
for (;;) {
|
||||
/* check urgent tasks */
|
||||
for (i = &m_idleTask; i != NULL; i = i->next) {
|
||||
if (i->state != TASK_STATE_RUNNING)
|
||||
continue;
|
||||
|
||||
if (i->priority > priority && i->counter) {
|
||||
priority = i->priority;
|
||||
next = i;
|
||||
}
|
||||
if (!i->state && i->counter > priority) {
|
||||
priority = i->priority;
|
||||
next = i;
|
||||
}
|
||||
}
|
||||
|
||||
if (next) {
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = &m_idleTask; i != NULL; i = i->next) {
|
||||
i->counter = i->cycles;
|
||||
}
|
||||
}
|
||||
|
||||
return next;
|
||||
}
|
||||
|
||||
void
|
||||
Task_initSheduler(void)
|
||||
{
|
||||
struct Task *idleTask = &m_idleTask;
|
||||
m_currentTask = idleTask;
|
||||
m_lastTask = m_currentTask;
|
||||
}
|
||||
|
||||
PID
|
||||
Task_create(TaskCallback callback, void *arg)
|
||||
{
|
||||
struct Task *task = Memory_getPage();
|
||||
|
||||
task->sp = (void *)task + MEMORY_PAGE_SIZE - 272;
|
||||
task->stackStart = task->sp;
|
||||
task->stackSize = MEMORY_PAGE_SIZE - sizeof(*task);
|
||||
task->lock = 1;
|
||||
task->counter = 1;
|
||||
task->cycles = 1;
|
||||
task->priority = 0;
|
||||
task->state = TASK_STATE_RUNNING;
|
||||
task->name[0] = 'N';
|
||||
task->name[1] = 'O';
|
||||
task->name[2] = 'N';
|
||||
task->name[3] = 'E';
|
||||
task->name[4] = 0;
|
||||
task->next = 0;
|
||||
|
||||
Task_lockScheduler();
|
||||
m_lastTask->next = task;
|
||||
m_lastTask = task;
|
||||
Task_unlockScheduler();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
Task_yield(void)
|
||||
{
|
||||
struct Task *next;
|
||||
|
||||
Task_lockScheduler();
|
||||
m_currentTask->counter = 0;
|
||||
|
||||
next = scheduleNext();
|
||||
|
||||
if (next != m_currentTask) {
|
||||
AArch64_switchContext(m_currentTask, next);
|
||||
m_currentTask = next;
|
||||
} else {
|
||||
__asm__("WFE");
|
||||
}
|
||||
|
||||
Task_unlockScheduler();
|
||||
}
|
||||
|
||||
void
|
||||
Task_lockScheduler(void)
|
||||
{
|
||||
m_currentTask->lock++;
|
||||
}
|
||||
|
||||
void
|
||||
Task_unlockScheduler(void)
|
||||
{
|
||||
m_currentTask->lock--;
|
||||
}
|
||||
|
||||
void *
|
||||
Task_scheduleFromISR(void)
|
||||
{
|
||||
void *sp = NULL;
|
||||
|
||||
if (!m_currentTask->lock) {
|
||||
struct Task *next;
|
||||
|
||||
Task_lockScheduler();
|
||||
next = scheduleNext();
|
||||
if (next != m_currentTask) {
|
||||
m_currentTask = next;
|
||||
sp = next->sp;
|
||||
}
|
||||
/* unlock call could be moved to aarch64.S interrupt handler in case of
|
||||
* issue
|
||||
* */
|
||||
Task_unlockScheduler();
|
||||
}
|
||||
|
||||
return sp;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,19 +24,22 @@
|
|||
|
||||
typedef void (*TaskCallback)(void *p_ctx);
|
||||
|
||||
struct Task {
|
||||
char name[CONFIG_TASK_MAX_NAME_LEN + 1];
|
||||
TaskCallback callback;
|
||||
uint64_t *stack;
|
||||
uint32_t stack_size;
|
||||
uint32_t priority;
|
||||
};
|
||||
void
|
||||
Task_initSheduler(void);
|
||||
|
||||
PID
|
||||
Task_create(struct Task *pTask, TaskCallback callback, uint64_t *stack
|
||||
, uint32_t stack_size);
|
||||
Task_create(TaskCallback callback, void *arg);
|
||||
|
||||
unsigned long
|
||||
void
|
||||
Task_yield(void);
|
||||
|
||||
void
|
||||
Task_lockScheduler(void);
|
||||
|
||||
void
|
||||
Task_unlockScheduler(void);
|
||||
|
||||
void *
|
||||
Task_scheduleFromISR(void);
|
||||
|
||||
#endif /* !TASK_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue