Add vector table

kernel/device/uart/uart.h

@@ -0,0 +1,47 @@
+/******************************************************************************
+ *
+ *                Copyright (c) 2017-2019 by Löwenware Ltd
+ *             Please, refer LICENSE file for legal information
+ *
+ ******************************************************************************/
+
+/**
+ * @file uart.h
+ * @author Ilja Kartašov <ik@lowenware.com>
+ * @brief 
+ *
+ * @see https://lowenware.com/
+ */
+
+#ifndef UART_H_8AFC47F9_2953_42C1_A5C1_1AE5A1F52CD0
+#define UART_H_8AFC47F9_2953_42C1_A5C1_1AE5A1F52CD0
+
+#include "uart_mini.h"
+#include "uart_qemu.h"
+
+#define UART_MINI 0
+#define UART_QEMU 1
+
+#ifndef UART_DEFAULT
+#define UART_DEFAULT UART_QEMU
+#endif
+
+#if UART_DEFAULT == UART_MINI
+
+#define uart_init(...) uart_mini_init(__VA_ARGS__)
+#define uart_read(...) uart_mini_read(__VA_ARGS__)
+#define uart_write(...) uart_mini_write(__VA_ARGS__)
+
+#elif UART_DEFAULT == UART_QEMU
+
+#define uart_init(...)
+#define uart_read(...)
+#define uart_write(...) uart_qemu_write(__VA_ARGS__)
+
+#else
+
+#warning "Unsopported default UART"
+
+#endif
+
+#endif /* !UART_H */

kernel/device/uart/uart_mini.c

@@ -0,0 +1,82 @@
+/******************************************************************************
+ *
+ *                Copyright (c) 2017-2019 by Löwenware Ltd
+ *             Please, refer LICENSE file for legal information
+ *
+ ******************************************************************************/
+
+/**
+ * @file uart_mini.c
+ * @author Ilja Kartašov <ik@lowenware.com>
+ * @brief 
+ *
+ * @see https://lowenware.com/
+ */
+
+#include <aarch64/aarch64.h>
+#include <aarch64/bcm2837.h>
+
+#include "uart_mini.h"
+
+
+int
+uart_mini_init(void)
+{
+	unsigned int sel;
+
+	/* Enable UART Mini and its registers*/
+	aarch64_set32r(AUX_ENABLES, 1);
+	/* Disable auto flow control, TX and RX */
+	aarch64_set32r(AUX_MU_CNTL_REG, 0);
+	/* Disable TX and RX interrupts */
+	aarch64_set32r(AUX_MU_IER_REG, 0);
+	/* Set 8bit mode */
+	aarch64_set32r(AUX_MU_LCR_REG, 0);
+	/* Set RTS line HIGH */
+	aarch64_set32r(AUX_MU_MCR_REG, 0);
+	/* Set baud rate 115200 */
+	aarch64_set32r(AUX_MU_BAUD_REG, 0x10E);
+
+	sel = aarch64_get32r(GPFSEL1);
+	/* clean and set ALT5 for GPIO14 */
+	sel &= ~(7 << 12);
+	sel |= (2 << 12);
+	/* clean and set ALT5 for GPIO15 */
+	sel &= ~(7 << 15);
+	sel |= (2 << 15);
+	aarch64_set32r(GPFSEL1, sel);
+
+	aarch64_set32r(GPPUD, 0);
+	aarch64_delay(150);
+	aarch64_set32r(GPPUDCLK0, (1 << 14) | (1 << 15));
+	aarch64_delay(150);
+	aarch64_set32r(GPPUDCLK0, 0);
+
+	/* Enable TX and RX */
+	aarch64_set32r(AUX_MU_CNTL_REG, 0x03);
+
+	return 0;
+}
+
+int
+uart_mini_write(char c)
+{
+	while (1) {
+		if (aarch64_get32r(AUX_MU_LSR_REG) & 0x20)
+			break;
+	}
+	aarch64_set32r(AUX_MU_IO_REG, c);
+
+	return 0;
+}
+
+int
+uart_mini_read(char *pc)
+{
+	while (1) {
+		if (aarch64_get32r(AUX_MU_LSR_REG) & 0x01)
+			break;
+	}
+	*pc = aarch64_get32r(AUX_MU_IO_REG) & 0xFF;
+	return 0;
+}

kernel/device/uart/uart_mini.h

@@ -0,0 +1,28 @@
+/******************************************************************************
+ *
+ *                Copyright (c) 2017-2019 by Löwenware Ltd
+ *             Please, refer LICENSE file for legal information
+ *
+ ******************************************************************************/
+
+/**
+ * @file uart_mini.h
+ * @author Ilja Kartašov <ik@lowenware.com>
+ * @brief 
+ *
+ * @see https://lowenware.com/
+ */
+
+#ifndef UART_MINI_H_B0DFA3CF_5B4F_4EB0_B393_391C0069A04F
+#define UART_MINI_H_B0DFA3CF_5B4F_4EB0_B393_391C0069A04F
+
+int
+uart_mini_init(void);
+
+int
+uart_mini_write(char c);
+
+int
+uart_mini_read(char *pc);
+
+#endif /* !UART_MINI_H */

kernel/device/uart/uart_qemu.c

@@ -0,0 +1,30 @@
+/******************************************************************************
+ *
+ *                Copyright (c) 2017-2019 by Löwenware Ltd
+ *             Please, refer LICENSE file for legal information
+ *
+ ******************************************************************************/
+
+/**
+ * @file uart.c
+ * @author Ilja Kartašov <ik@lowenware.com>
+ * @brief 
+ *
+ * @see https://lowenware.com/
+ */
+
+#include "uart_qemu.h"
+
+#define UART_BASE 0x09000000;
+
+volatile unsigned int *UART0 = (unsigned int *)UART_BASE;
+
+int
+uart_qemu_write(unsigned char c)
+{
+	*UART0 = (unsigned int) c;
+	return 0;
+}
+
+
+

kernel/device/uart/uart_qemu.h

@@ -0,0 +1,22 @@
+/******************************************************************************
+ *
+ *                Copyright (c) 2017-2019 by Löwenware Ltd
+ *             Please, refer LICENSE file for legal information
+ *
+ ******************************************************************************/
+
+/**
+ * @file uart_qemu.h
+ * @author Ilja Kartašov <ik@lowenware.com>
+ * @brief 
+ *
+ * @see https://lowenware.com/
+ */
+
+#ifndef UART_QEMU_H_EDB39A0E_9BED_4A47_91CD_E804A9B4E8ED
+#define UART_QEMU_H_EDB39A0E_9BED_4A47_91CD_E804A9B4E8ED
+
+int
+uart_qemu_write(unsigned char c);
+
+#endif /* !UART_QEMU_H */