164 lines
6.0 KiB
C
164 lines
6.0 KiB
C
/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file aarch64_reg.h
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#ifndef AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
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#define AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
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#define AARCH64_LOCAL_INT_ROUTING *((uint32_t *) 0x40000024)
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#define AARCH64_LOCAL_TIMER_STATCTL *((uint32_t *) 0x40000034)
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#define AARCH64_LOCAL_TIMER_RECLR *((uint32_t *) 0x40000038)
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/* Timers interrupt control registers
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* */
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#define AARCH64_CORE0_TIMER_IRQCTL *((uint32_t *) 0x40000040)
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#define AARCH64_CORE1_TIMER_IRQCTL *((uint32_t *) 0x40000044)
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#define AARCH64_CORE2_TIMER_IRQCTL *((uint32_t *) 0x40000048)
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#define AARCH64_CORE3_TIMER_IRQCTL *((uint32_t *) 0x4000004C)
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/* Timer interrupr routing
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* */
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#define AARCH64_TIMER0_IRQ 0x01
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#define AARCH64_TIMER1_IRQ 0x02
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#define AARCH64_TIMER2_IRQ 0x04
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#define AARCH64_TIMER3_IRQ 0x08
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#define AARCH64_TIMER0_FIQ 0x10
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#define AARCH64_TIMER1_FIQ 0x20
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#define AARCH64_TIMER2_FIQ 0x40
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#define AARCH64_TIMER3_FIQ 0x80
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/* Mailbox control registers
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* */
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#define AARCH64_CORE0_MBOX_IRQCTL *((uint32_t *) 0x40000050)
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#define AARCH64_CORE1_MBOX_IRQCTL *((uint32_t *) 0x40000054)
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#define AARCH64_CORE2_MBOX_IRQCTL *((uint32_t *) 0x40000058)
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#define AARCH64_CORE3_MBOX_IRQCTL *((uint32_t *) 0x4000005C)
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/* Mailbox interrupr routing
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* */
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#define AARCH64_MBOX0_IRQ 0x01
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#define AARCH64_MBOX1_IRQ 0x02
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#define AARCH64_MBOX2_IRQ 0x04
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#define AARCH64_MBOX3_IRQ 0x08
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#define AARCH64_MBOX0_FIQ 0x10
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#define AARCH64_MBOX1_FIQ 0x20
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#define AARCH64_MBOX2_FIQ 0x40
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#define AARCH64_MBOX3_FIQ 0x80
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/* Source registers for IRQ / FIQ
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* */
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#define AARCH64_CORE0_IRQSRC *((uint32_t *) 0x40000060)
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#define AARCH64_CORE1_IRQSRC *((uint32_t *) 0x40000064)
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#define AARCH64_CORE2_IRQSRC *((uint32_t *) 0x40000068)
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#define AARCH64_CORE3_IRQSRC *((uint32_t *) 0x4000006C)
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#define AARCH64_CORE0_FIQSRC *((uint32_t *) 0x40000070)
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#define AARCH64_CORE1_FIQSRC *((uint32_t *) 0x40000074)
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#define AARCH64_CORE2_FIQSRC *((uint32_t *) 0x40000078)
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#define AARCH64_CORE3_FIQSRC *((uint32_t *) 0x4000007C)
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/* Interrupt source bits
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* */
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#define AARCH64_TIMER0_INTSRC 0x0001
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#define AARCH64_TIMER1_INTSRC 0x0002
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#define AARCH64_TIMER2_INTSRC 0x0004
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#define AARCH64_TIMER3_INTSRC 0x0008
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#define AARCH64_MBOX0_INTSRC 0x0010
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#define AARCH64_MBOX1_INTSRC 0x0020
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#define AARCH64_MBOX2_INTSRC 0x0040
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#define AARCH64_MBOX3_INTSRC 0x0080
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#define AARCH64_GPU_INTSRC 0x0100
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#define AARCH64_PMU_INTSRC 0x0200
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/* Mailbox write-set registers (write only)
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* */
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#define AARCH64_CORE0_MBOX0_SETREG *((uint32_t *) 0x40000080)
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#define AARCH64_CORE0_MBOX1_SETREG *((uint32_t *) 0x40000084)
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#define AARCH64_CORE0_MBOX2_SETREG *((uint32_t *) 0x40000088)
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#define AARCH64_CORE0_MBOX3_SETREG *((uint32_t *) 0x4000008C)
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#define AARCH64_CORE1_MBOX0_SETREG *((uint32_t *) 0x40000090)
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#define AARCH64_CORE1_MBOX1_SETREG *((uint32_t *) 0x40000094)
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#define AARCH64_CORE1_MBOX2_SETREG *((uint32_t *) 0x40000098)
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#define AARCH64_CORE1_MBOX3_SETREG *((uint32_t *) 0x4000009C)
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#define AARCH64_CORE2_MBOX0_SETREG *((uint32_t *) 0x400000A0)
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#define AARCH64_CORE2_MBOX1_SETREG *((uint32_t *) 0x400000A4)
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#define AARCH64_CORE2_MBOX2_SETREG *((uint32_t *) 0x400000A8)
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#define AARCH64_CORE2_MBOX3_SETREG *((uint32_t *) 0x400000AC)
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#define AARCH64_CORE3_MBOX0_SETREG *((uint32_t *) 0x400000B0)
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#define AARCH64_CORE3_MBOX1_SETREG *((uint32_t *) 0x400000B4)
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#define AARCH64_CORE3_MBOX2_SETREG *((uint32_t *) 0x400000B8)
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#define AARCH64_CORE3_MBOX3_SETREG *((uint32_t *) 0x400000BC)
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/* Mailbox write-clear registers (Read & Write)
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* */
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#define AARCH64_CORE0_MBOX0_RDCLREG *((uint32_t *) 0x400000C0)
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#define AARCH64_CORE0_MBOX1_RDCLREG *((uint32_t *) 0x400000C4)
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#define AARCH64_CORE0_MBOX2_RDCLREG *((uint32_t *) 0x400000C8)
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#define AARCH64_CORE0_MBOX3_RDCLREG *((uint32_t *) 0x400000CC)
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#define AARCH64_CORE1_MBOX0_RDCLREG *((uint32_t *) 0x400000D0)
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#define AARCH64_CORE1_MBOX1_RDCLREG *((uint32_t *) 0x400000D4)
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#define AARCH64_CORE1_MBOX2_RDCLREG *((uint32_t *) 0x400000D8)
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#define AARCH64_CORE1_MBOX3_RDCLREG *((uint32_t *) 0x400000DC)
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#define AARCH64_CORE2_MBOX0_RDCLREG *((uint32_t *) 0x400000E0)
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#define AARCH64_CORE2_MBOX1_RDCLREG *((uint32_t *) 0x400000E4)
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#define AARCH64_CORE2_MBOX2_RDCLREG *((uint32_t *) 0x400000E8)
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#define AARCH64_CORE2_MBOX3_RDCLREG *((uint32_t *) 0x400000EC)
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#define AARCH64_CORE3_MBOX0_RDCLREG *((uint32_t *) 0x400000F0)
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#define AARCH64_CORE3_MBOX1_RDCLREG *((uint32_t *) 0x400000F4)
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#define AARCH64_CORE3_MBOX2_RDCLREG *((uint32_t *) 0x400000F8)
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#define AARCH64_CORE3_MBOX3_RDCLREG *((uint32_t *) 0x400000FC)
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/* Saved Program Status Register (SPSR)
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* Exception Level 3 (EL3)
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* See page 389 of AArch64-Reference-Manual
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* */
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#define SPSR_MASK_ALL (7 << 6)
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#define SPSR_EL1h (5 << 0)
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#define SPSR_VALUE (SPSR_MASK_ALL | SPSR_EL1h)
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/* Secure Configuration Register (SCR)
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* Exception Level 3 (EL3)
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* See page 2648 of AArch64-Reference-Manual
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* */
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#define SCR_RESERVED (3 << 4)
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#define SCR_RW (1 << 10)
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#define SCR_NS (1 << 0)
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#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_NS)
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/* Hypervisor Configuration Register (HCR)
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* Exception Level 2 (EL2)
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* See page 2487 of AArch64-Reference-Manual
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* */
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#define HCR_RW (1 << 31)
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#define HCR_VALUE HCR_RW
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/* System Control REgister (SCTLR_EL1)
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* Exception Level 1 (EL1)
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* See page 2654 of AArch64-Reference-Manual
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* */
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#define SCTLR_RESERVED (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)
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#define SCTLR_EE_LITTLE_ENDIAN (0 << 25)
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#define SCTLR_EOE_LITTLE_ENDIAN (0 << 24)
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#define SCTLR_I_CACHE_DISABLED (0 << 12)
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#define SCTLR_D_CACHE_DISABLED (0 << 2)
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#define SCTLR_MMU_DISABLED (0 << 0)
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#define SCTLR_MMU_ENABLED (1 << 0)
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#define SCTLR_VALUE_MMU_DISABLED (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN \
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| SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)
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#endif /* !AARCH64_REG_H */
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