85 lines
1.8 KiB
C
85 lines
1.8 KiB
C
/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file UARTMini.c
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#include <aarch64/aarch64.h>
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#include <drivers/soc/bcm2837/bcm2837.h>
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#include "uart_mini.h"
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int
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UARTMini_init(void)
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{
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unsigned int sel;
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/* Enable UART Mini and its registers*/
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AArch64_setReg32(AUX_ENABLES, 1);
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/* Disable TX and RX interrupts */
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AArch64_setReg32(AUX_MU_IER_REG, 0);
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/* Disable auto flow control, TX and RX */
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AArch64_setReg32(AUX_MU_CNTL_REG, 0);
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/* Set 8bit mode */
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AArch64_setReg32(AUX_MU_LCR_REG, 3);
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/* Set RTS line HIGH */
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AArch64_setReg32(AUX_MU_MCR_REG, 0);
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/* Set baud rate 115200 */
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AArch64_setReg32(AUX_MU_IER_REG, 0);
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AArch64_setReg32(AUX_MU_IIR_REG, 0xC6);
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AArch64_setReg32(AUX_MU_BAUD_REG, 270);
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sel = AArch64_getReg32(GPFSEL1);
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/* clean and set ALT5 for GPIO14 */
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sel &= ~(7 << 12);
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sel |= (2 << 12);
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/* clean and set ALT5 for GPIO15 */
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sel &= ~(7 << 15);
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sel |= (2 << 15);
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AArch64_setReg32(GPFSEL1, sel);
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AArch64_setReg32(GPPUD, 0);
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AArch64_idle(150);
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AArch64_setReg32(GPPUDCLK0, (1 << 14) | (1 << 15));
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AArch64_idle(150);
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AArch64_setReg32(GPPUDCLK0, 0);
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/* Enable TX and RX */
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AArch64_setReg32(AUX_MU_CNTL_REG, 3);
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return 0;
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}
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int
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UARTMini_put(char c)
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{
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while (1) {
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if (AArch64_getReg32(AUX_MU_LSR_REG) & 0x20)
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break;
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}
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AArch64_setReg32(AUX_MU_IO_REG, c);
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return 0;
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}
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int
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UARTMini_get(char *pc)
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{
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while (1) {
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if (AArch64_getReg32(AUX_MU_LSR_REG) & 0x01)
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break;
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}
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*pc = AArch64_getReg32(AUX_MU_IO_REG) & 0xFF;
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return 0;
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}
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