os-core/kernel/device/uart/uart_mini.c

85 lines
1.7 KiB
C

/******************************************************************************
*
* Copyright (c) 2017-2019 by Löwenware Ltd
* Please, refer LICENSE file for legal information
*
******************************************************************************/
/**
* @file uart_mini.c
* @author Ilja Kartašov <ik@lowenware.com>
* @brief
*
* @see https://lowenware.com/
*/
#include <aarch64/aarch64.h>
#include <aarch64/bcm2837.h>
#include "uart_mini.h"
int
uart_mini_init(void)
{
unsigned int sel;
/* Enable UART Mini and its registers*/
aarch64_set32r(AUX_ENABLES, 1);
/* Disable TX and RX interrupts */
aarch64_set32r(AUX_MU_IER_REG, 0);
/* Disable auto flow control, TX and RX */
aarch64_set32r(AUX_MU_CNTL_REG, 0);
/* Set 8bit mode */
aarch64_set32r(AUX_MU_LCR_REG, 3);
/* Set RTS line HIGH */
aarch64_set32r(AUX_MU_MCR_REG, 0);
/* Set baud rate 115200 */
aarch64_set32r(AUX_MU_IER_REG, 0);
aarch64_set32r(AUX_MU_IIR_REG, 0xC6);
aarch64_set32r(AUX_MU_BAUD_REG, 270);
sel = aarch64_get32r(GPFSEL1);
/* clean and set ALT5 for GPIO14 */
sel &= ~(7 << 12);
sel |= (2 << 12);
/* clean and set ALT5 for GPIO15 */
sel &= ~(7 << 15);
sel |= (2 << 15);
aarch64_set32r(GPFSEL1, sel);
aarch64_set32r(GPPUD, 0);
aarch64_delay(150);
aarch64_set32r(GPPUDCLK0, (1 << 14) | (1 << 15));
aarch64_delay(150);
aarch64_set32r(GPPUDCLK0, 0);
/* Enable TX and RX */
aarch64_set32r(AUX_MU_CNTL_REG, 3);
return 0;
}
int
uart_mini_write(char c)
{
while (1) {
if (aarch64_get32r(AUX_MU_LSR_REG) & 0x20)
break;
}
aarch64_set32r(AUX_MU_IO_REG, c);
return 0;
}
int
uart_mini_read(char *pc)
{
while (1) {
if (aarch64_get32r(AUX_MU_LSR_REG) & 0x01)
break;
}
*pc = aarch64_get32r(AUX_MU_IO_REG) & 0xFF;
return 0;
}