os-core/kernel/aarch64/aarch64_reg.h

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2019-12-01 22:57:02 +01:00
/******************************************************************************
*
* Copyright (c) 2017-2019 by Löwenware Ltd
* Please, refer LICENSE file for legal information
*
******************************************************************************/
/**
* @file aarch64_reg.h
* @author Ilja Kartašov <ik@lowenware.com>
* @brief
*
* @see https://lowenware.com/
*/
#ifndef AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
#define AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
/* Saved Program Status Register (SPSR)
* Exception Level 3 (EL3)
* See page 389 of AArch64-Reference-Manual
* */
#define SPSR_MASK_ALL (7 << 6)
#define SPSR_EL1h (5 << 0)
#define SPSR_VALUE (SPSR_MASK_ALL | SPSR_EL1h)
/* Secure Configuration Register (SCR)
* Exception Level 3 (EL3)
* See page 2648 of AArch64-Reference-Manual
* */
#define SCR_RESERVED (3 << 4)
#define SCR_RW (1 << 10)
#define SCR_NS (1 << 0)
#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_NS)
/* Hypervisor Configuration Register (HCR)
* Exception Level 2 (EL2)
* See page 2487 of AArch64-Reference-Manual
* */
#define HCR_RW (1 << 31)
#define HCR_VALUE HCR_RW
/* System Control REgister (SCTLR_EL1)
* Exception Level 1 (EL1)
* See page 2654 of AArch64-Reference-Manual
* */
#define SCTLR_RESERVED (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)
#define SCTLR_EE_LITTLE_ENDIAN (0 << 25)
#define SCTLR_EOE_LITTLE_ENDIAN (0 << 24)
#define SCTLR_I_CACHE_DISABLED (0 << 12)
#define SCTLR_D_CACHE_DISABLED (0 << 2)
#define SCTLR_MMU_DISABLED (0 << 0)
#define SCTLR_MMU_ENABLED (1 << 0)
#define SCTLR_VALUE_MMU_DISABLED (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN \
| SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)
#endif /* !AARCH64_REG_H */