60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file aarch64_reg.h
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#ifndef AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
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#define AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
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/* Saved Program Status Register (SPSR)
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* Exception Level 3 (EL3)
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* See page 389 of AArch64-Reference-Manual
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* */
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#define SPSR_MASK_ALL (7 << 6)
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#define SPSR_EL1h (5 << 0)
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#define SPSR_VALUE (SPSR_MASK_ALL | SPSR_EL1h)
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/* Secure Configuration Register (SCR)
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* Exception Level 3 (EL3)
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* See page 2648 of AArch64-Reference-Manual
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* */
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#define SCR_RESERVED (3 << 4)
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#define SCR_RW (1 << 10)
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#define SCR_NS (1 << 0)
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#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_NS)
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/* Hypervisor Configuration Register (HCR)
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* Exception Level 2 (EL2)
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* See page 2487 of AArch64-Reference-Manual
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* */
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#define HCR_RW (1 << 31)
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#define HCR_VALUE HCR_RW
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/* System Control REgister (SCTLR_EL1)
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* Exception Level 1 (EL1)
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* See page 2654 of AArch64-Reference-Manual
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* */
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#define SCTLR_RESERVED (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)
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#define SCTLR_EE_LITTLE_ENDIAN (0 << 25)
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#define SCTLR_EOE_LITTLE_ENDIAN (0 << 24)
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#define SCTLR_I_CACHE_DISABLED (0 << 12)
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#define SCTLR_D_CACHE_DISABLED (0 << 2)
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#define SCTLR_MMU_DISABLED (0 << 0)
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#define SCTLR_MMU_ENABLED (1 << 0)
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#define SCTLR_VALUE_MMU_DISABLED (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN \
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| SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)
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#endif /* !AARCH64_REG_H */
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