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Add context switching and basic scheduler

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This commit is contained in:
elias
2020-01-20 09:14:13 +01:00
parent a93f257f2e
commit 26f05b04d7
13 changed files with 410 additions and 27 deletions
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kernel/aarch64/aarch64.S
+55 -2
View File
@@ -56,7 +56,7 @@ AArch64_memzero:
/* Exceptions Vector Table
* */
.macro SAVE_REGISTERS
sub sp, sp, 256
sub sp, sp, 272
stp x0, x1, [sp, 16 * 0]
stp x2, x3, [sp, 16 * 1]
stp x4, x5, [sp, 16 * 2]
@@ -102,7 +102,7 @@ AArch64_memzero:
ldp x4, x5, [sp, 16 * 2]
ldp x2, x3, [sp, 16 * 1]
ldp x0, x1, [sp, 16 * 0]
add sp, sp, 256
add sp, sp, 272
.endm
.macro VECTOR_ENTRY GOTO_LABEL
@@ -122,6 +122,59 @@ AArch64_memzero:
die:
b die
.globl AArch64_switchContext
AArch64_switchContext:
/* Save current task context */
sub sp, sp, 272
stp x0, x1, [sp, 16 * 0]
stp x2, x3, [sp, 16 * 1]
stp x4, x5, [sp, 16 * 2]
stp x6, x7, [sp, 16 * 3]
stp x8, x9, [sp, 16 * 4]
stp x10, x11, [sp, 16 * 5]
stp x12, x13, [sp, 16 * 6]
stp x14, x15, [sp, 16 * 7]
stp x16, x17, [sp, 16 * 8]
stp x18, x19, [sp, 16 * 9]
stp x20, x21, [sp, 16 * 10]
stp x22, x23, [sp, 16 * 11]
stp x24, x25, [sp, 16 * 12]
stp x26, x27, [sp, 16 * 13]
stp x28, x29, [sp, 16 * 14]
mrs x23, NZCV
mrs x3, DAIF
orr x23, x23, x3
mrs x3, CurrentEL
orr x23, x23, x3
stp x30, x30, [sp, 16 * 15]
str x23, [sp, 16 * 16]
mov x2, sp
str x2, [x0]
/* Restore next task context */
ldr x2, [x1]
mov sp, x2
ldr x30, [sp, 16 * 15]
ldp x28, x29, [sp, 16 * 14]
ldp x26, x27, [sp, 16 * 13]
ldp x24, x25, [sp, 16 * 12]
ldp x22, x23, [sp, 16 * 11]
ldp x20, x21, [sp, 16 * 10]
ldp x18, x19, [sp, 16 * 9]
ldp x16, x17, [sp, 16 * 8]
ldp x14, x15, [sp, 16 * 7]
ldp x12, x13, [sp, 16 * 6]
ldp x10, x11, [sp, 16 * 5]
ldp x8, x9, [sp, 16 * 4]
ldp x6, x7, [sp, 16 * 3]
ldp x4, x5, [sp, 16 * 2]
ldp x2, x3, [sp, 16 * 1]
ldp x0, x1, [sp, 16 * 0]
add sp, sp, 272
ret
.align 11
.globl AArch64_vectors
AArch64_vectors:
kernel/aarch64/aarch64.h
+3
View File
@@ -43,4 +43,7 @@ AArch64_disableIRQ(void);
extern void
AArch64_memzero(void *addr, unsigned long size);
extern void
AArch64_switchContext(void *currentTask, void *nextTask);
#endif /* !AARCH64_H */
kernel/aarch64/aarch64.ld
+2 -2
View File
@@ -10,6 +10,6 @@ SECTIONS
bss_end = .;
. = ALIGN(8);
. = . + 0x8000;
stack_ptr = . ;
. = . + 0x4000;
ld_stackPtr = . ;
}
kernel/aarch64/aarch64_boot.S
+1 -1
View File
@@ -31,7 +31,7 @@ set_el:
eret
set_stack:
ldr x30, =stack_ptr /* defined in aarch64.ld */
ldr x30, =ld_stackPtr /* defined in aarch64.ld */
mov sp, x30
bl skip
skip:
kernel/aarch64/aarch64_reg.h
+104
View File
@@ -16,6 +16,110 @@
#ifndef AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
#define AARCH64_REG_H_C74FE7BF_C8A6_4718_867A_C125CBF326BD
#define AARCH64_LOCAL_INT_ROUTING *((uint32_t *) 0x40000024)
#define AARCH64_LOCAL_TIMER_STATCTL *((uint32_t *) 0x40000034)
#define AARCH64_LOCAL_TIMER_RECLR *((uint32_t *) 0x40000038)
/* Timers interrupt control registers
* */
#define AARCH64_CORE0_TIMER_IRQCTL *((uint32_t *) 0x40000040)
#define AARCH64_CORE1_TIMER_IRQCTL *((uint32_t *) 0x40000044)
#define AARCH64_CORE2_TIMER_IRQCTL *((uint32_t *) 0x40000048)
#define AARCH64_CORE3_TIMER_IRQCTL *((uint32_t *) 0x4000004C)
/* Timer interrupr routing
* */
#define AARCH64_TIMER0_IRQ 0x01
#define AARCH64_TIMER1_IRQ 0x02
#define AARCH64_TIMER2_IRQ 0x04
#define AARCH64_TIMER3_IRQ 0x08
#define AARCH64_TIMER0_FIQ 0x10
#define AARCH64_TIMER1_FIQ 0x20
#define AARCH64_TIMER2_FIQ 0x40
#define AARCH64_TIMER3_FIQ 0x80
/* Mailbox control registers
* */
#define AARCH64_CORE0_MBOX_IRQCTL *((uint32_t *) 0x40000050)
#define AARCH64_CORE1_MBOX_IRQCTL *((uint32_t *) 0x40000054)
#define AARCH64_CORE2_MBOX_IRQCTL *((uint32_t *) 0x40000058)
#define AARCH64_CORE3_MBOX_IRQCTL *((uint32_t *) 0x4000005C)
/* Mailbox interrupr routing
* */
#define AARCH64_MBOX0_IRQ 0x01
#define AARCH64_MBOX1_IRQ 0x02
#define AARCH64_MBOX2_IRQ 0x04
#define AARCH64_MBOX3_IRQ 0x08
#define AARCH64_MBOX0_FIQ 0x10
#define AARCH64_MBOX1_FIQ 0x20
#define AARCH64_MBOX2_FIQ 0x40
#define AARCH64_MBOX3_FIQ 0x80
/* Source registers for IRQ / FIQ
* */
#define AARCH64_CORE0_IRQSRC *((uint32_t *) 0x40000060)
#define AARCH64_CORE1_IRQSRC *((uint32_t *) 0x40000064)
#define AARCH64_CORE2_IRQSRC *((uint32_t *) 0x40000068)
#define AARCH64_CORE3_IRQSRC *((uint32_t *) 0x4000006C)
#define AARCH64_CORE0_FIQSRC *((uint32_t *) 0x40000070)
#define AARCH64_CORE1_FIQSRC *((uint32_t *) 0x40000074)
#define AARCH64_CORE2_FIQSRC *((uint32_t *) 0x40000078)
#define AARCH64_CORE3_FIQSRC *((uint32_t *) 0x4000007C)
/* Interrupt source bits
* */
#define AARCH64_TIMER0_INTSRC 0x0001
#define AARCH64_TIMER1_INTSRC 0x0002
#define AARCH64_TIMER2_INTSRC 0x0004
#define AARCH64_TIMER3_INTSRC 0x0008
#define AARCH64_MBOX0_INTSRC 0x0010
#define AARCH64_MBOX1_INTSRC 0x0020
#define AARCH64_MBOX2_INTSRC 0x0040
#define AARCH64_MBOX3_INTSRC 0x0080
#define AARCH64_GPU_INTSRC 0x0100
#define AARCH64_PMU_INTSRC 0x0200
/* Mailbox write-set registers (write only)
* */
#define AARCH64_CORE0_MBOX0_SETREG *((uint32_t *) 0x40000080)
#define AARCH64_CORE0_MBOX1_SETREG *((uint32_t *) 0x40000084)
#define AARCH64_CORE0_MBOX2_SETREG *((uint32_t *) 0x40000088)
#define AARCH64_CORE0_MBOX3_SETREG *((uint32_t *) 0x4000008C)
#define AARCH64_CORE1_MBOX0_SETREG *((uint32_t *) 0x40000090)
#define AARCH64_CORE1_MBOX1_SETREG *((uint32_t *) 0x40000094)
#define AARCH64_CORE1_MBOX2_SETREG *((uint32_t *) 0x40000098)
#define AARCH64_CORE1_MBOX3_SETREG *((uint32_t *) 0x4000009C)
#define AARCH64_CORE2_MBOX0_SETREG *((uint32_t *) 0x400000A0)
#define AARCH64_CORE2_MBOX1_SETREG *((uint32_t *) 0x400000A4)
#define AARCH64_CORE2_MBOX2_SETREG *((uint32_t *) 0x400000A8)
#define AARCH64_CORE2_MBOX3_SETREG *((uint32_t *) 0x400000AC)
#define AARCH64_CORE3_MBOX0_SETREG *((uint32_t *) 0x400000B0)
#define AARCH64_CORE3_MBOX1_SETREG *((uint32_t *) 0x400000B4)
#define AARCH64_CORE3_MBOX2_SETREG *((uint32_t *) 0x400000B8)
#define AARCH64_CORE3_MBOX3_SETREG *((uint32_t *) 0x400000BC)
/* Mailbox write-clear registers (Read & Write)
* */
#define AARCH64_CORE0_MBOX0_RDCLREG *((uint32_t *) 0x400000C0)
#define AARCH64_CORE0_MBOX1_RDCLREG *((uint32_t *) 0x400000C4)
#define AARCH64_CORE0_MBOX2_RDCLREG *((uint32_t *) 0x400000C8)
#define AARCH64_CORE0_MBOX3_RDCLREG *((uint32_t *) 0x400000CC)
#define AARCH64_CORE1_MBOX0_RDCLREG *((uint32_t *) 0x400000D0)
#define AARCH64_CORE1_MBOX1_RDCLREG *((uint32_t *) 0x400000D4)
#define AARCH64_CORE1_MBOX2_RDCLREG *((uint32_t *) 0x400000D8)
#define AARCH64_CORE1_MBOX3_RDCLREG *((uint32_t *) 0x400000DC)
#define AARCH64_CORE2_MBOX0_RDCLREG *((uint32_t *) 0x400000E0)
#define AARCH64_CORE2_MBOX1_RDCLREG *((uint32_t *) 0x400000E4)
#define AARCH64_CORE2_MBOX2_RDCLREG *((uint32_t *) 0x400000E8)
#define AARCH64_CORE2_MBOX3_RDCLREG *((uint32_t *) 0x400000EC)
#define AARCH64_CORE3_MBOX0_RDCLREG *((uint32_t *) 0x400000F0)
#define AARCH64_CORE3_MBOX1_RDCLREG *((uint32_t *) 0x400000F4)
#define AARCH64_CORE3_MBOX2_RDCLREG *((uint32_t *) 0x400000F8)
#define AARCH64_CORE3_MBOX3_RDCLREG *((uint32_t *) 0x400000FC)
/* Saved Program Status Register (SPSR)
* Exception Level 3 (EL3)
* See page 389 of AArch64-Reference-Manual