Update code due to new rules
This commit is contained in:
+66
-44
@@ -1,53 +1,61 @@
|
||||
#include "aarch64_irq.h"
|
||||
#include "AArch64_irq.h"
|
||||
|
||||
.globl aarch64_init
|
||||
aarch64_init:
|
||||
.globl AArch64_init
|
||||
AArch64_init:
|
||||
/* set vector table */
|
||||
adr x0, aarch64_vectors
|
||||
adr x0, AArch64_vectors
|
||||
msr vbar_el1, x0
|
||||
mov x0, 0
|
||||
ret
|
||||
|
||||
.globl aarch64_get_el
|
||||
aarch64_get_el:
|
||||
.globl AArch64_getEL
|
||||
AArch64_getEL:
|
||||
mrs x0, CurrentEL
|
||||
lsr x0, x0, 0x02
|
||||
ret
|
||||
|
||||
.globl aarch64_get32r
|
||||
aarch64_get32r:
|
||||
.globl AArch64_getReg32
|
||||
AArch64_get32r:
|
||||
ldr w0, [x0]
|
||||
ret
|
||||
|
||||
.globl aarch64_set32r
|
||||
aarch64_set32r:
|
||||
.globl AArch64_setReg32
|
||||
AArch64_set32r:
|
||||
str w1, [x0]
|
||||
ret
|
||||
|
||||
.globl aarch64_delay
|
||||
aarch64_delay:
|
||||
.globl AArch64_idle
|
||||
AArch64_idle:
|
||||
subs x0, x0, 1
|
||||
bne aarch64_delay
|
||||
bne AArch64_delay
|
||||
ret
|
||||
|
||||
.globl aarch64_irq_vector_init
|
||||
irq_vector_init:
|
||||
/*
|
||||
.globl AArch64_initIRQVector
|
||||
AArch64_initIRQVector:
|
||||
ret
|
||||
*/
|
||||
|
||||
.globl aarch64_irq_enable
|
||||
aarch64_irq_enable:
|
||||
.globl AArch64_enableIRQ
|
||||
AArch64_enableIRQ:
|
||||
msr daifclr, 2
|
||||
ret
|
||||
|
||||
.globl aarch64_irq_disable
|
||||
aarch64_irq_disable:
|
||||
.globl AArch64_disableIRQ
|
||||
AArch64_disableIRQ:
|
||||
msr daifset, 2
|
||||
ret
|
||||
|
||||
.globl AArch64_memzero
|
||||
AArch64_memzero:
|
||||
str xzr, [x0], 8
|
||||
subs x1, x1, 8
|
||||
b.gt AArch64_memzero
|
||||
ret
|
||||
|
||||
/* Exceptions Vector Table
|
||||
* */
|
||||
.macro KERNEL_ENTER
|
||||
.macro SAVE_REGISTERS
|
||||
sub sp, sp, 256
|
||||
stp x0, x1, [sp, 16 * 0]
|
||||
stp x2, x3, [sp, 16 * 1]
|
||||
@@ -64,26 +72,36 @@ aarch64_irq_disable:
|
||||
stp x24, x25, [sp, 16 * 12]
|
||||
stp x26, x27, [sp, 16 * 13]
|
||||
stp x28, x29, [sp, 16 * 14]
|
||||
str x30, [sp, 16 * 15]
|
||||
|
||||
mrs x22, elr_el1
|
||||
mrs x23, spsr_el1
|
||||
|
||||
stp x30, x22, [sp, 16 * 15]
|
||||
str x23, [sp, 16 * 16]
|
||||
.endm
|
||||
|
||||
.macro KERNEL_LEAVE
|
||||
ldp x0, x1, [sp, 16 * 0]
|
||||
ldp x2, x3, [sp, 16 * 1]
|
||||
ldp x4, x5, [sp, 16 * 2]
|
||||
ldp x6, x7, [sp, 16 * 3]
|
||||
ldp x8, x9, [sp, 16 * 4]
|
||||
ldp x10, x11, [sp, 16 * 5]
|
||||
ldp x12, x13, [sp, 16 * 6]
|
||||
ldp x14, x15, [sp, 16 * 7]
|
||||
ldp x16, x17, [sp, 16 * 8]
|
||||
ldp x18, x19, [sp, 16 * 9]
|
||||
ldp x20, x21, [sp, 16 * 10]
|
||||
ldp x22, x23, [sp, 16 * 11]
|
||||
ldp x24, x25, [sp, 16 * 12]
|
||||
ldp x26, x27, [sp, 16 * 13]
|
||||
.macro LOAD_REGISTERS
|
||||
ldr x23, [sp, 16 * 16]
|
||||
ldp x30, x22, [sp, 16 * 15]
|
||||
|
||||
msr elr_el1, x22
|
||||
msr spsr_el1, x23
|
||||
|
||||
ldp x28, x29, [sp, 16 * 14]
|
||||
ldr x30, [sp, 16 * 15]
|
||||
ldp x26, x27, [sp, 16 * 13]
|
||||
ldp x24, x25, [sp, 16 * 12]
|
||||
ldp x22, x23, [sp, 16 * 11]
|
||||
ldp x20, x21, [sp, 16 * 10]
|
||||
ldp x18, x19, [sp, 16 * 9]
|
||||
ldp x16, x17, [sp, 16 * 8]
|
||||
ldp x14, x15, [sp, 16 * 7]
|
||||
ldp x12, x13, [sp, 16 * 6]
|
||||
ldp x10, x11, [sp, 16 * 5]
|
||||
ldp x8, x9, [sp, 16 * 4]
|
||||
ldp x6, x7, [sp, 16 * 3]
|
||||
ldp x4, x5, [sp, 16 * 2]
|
||||
ldp x2, x3, [sp, 16 * 1]
|
||||
ldp x0, x1, [sp, 16 * 0]
|
||||
add sp, sp, 256
|
||||
.endm
|
||||
|
||||
@@ -93,11 +111,11 @@ aarch64_irq_disable:
|
||||
.endm
|
||||
|
||||
.macro EXCEPTION_FALLBACK EID
|
||||
KERNEL_ENTER
|
||||
SAVE_REGISTERS
|
||||
mov x0, \EID
|
||||
mrs x1, esr_el1
|
||||
mrs x2, elr_el1
|
||||
bl k_irq_fallback
|
||||
bl IRQ_fallback
|
||||
b die
|
||||
.endm
|
||||
|
||||
@@ -105,8 +123,8 @@ die:
|
||||
b die
|
||||
|
||||
.align 11
|
||||
.globl aarch64_vectors
|
||||
aarch64_vectors:
|
||||
.globl AArch64_vectors
|
||||
AArch64_vectors:
|
||||
/* EL1t */
|
||||
VECTOR_ENTRY el1t_sync
|
||||
VECTOR_ENTRY el1t_irq
|
||||
@@ -144,9 +162,12 @@ el1h_sync:
|
||||
EXCEPTION_FALLBACK EL1h_SYNC
|
||||
|
||||
el1h_irq:
|
||||
KERNEL_ENTER
|
||||
bl k_irq_handler
|
||||
KERNEL_LEAVE
|
||||
SAVE_REGISTERS
|
||||
bl IRQ_onInterrupt
|
||||
cbz x0, load_regs
|
||||
mov sp, x0 /* task context must be switched */
|
||||
load_regs:
|
||||
LOAD_REGISTERS
|
||||
eret
|
||||
|
||||
el1h_fiq:
|
||||
@@ -179,3 +200,4 @@ el0_32_fiq:
|
||||
el0_32_error:
|
||||
EXCEPTION_FALLBACK EL0_32_ERROR
|
||||
|
||||
|
||||
|
||||
@@ -20,24 +20,27 @@
|
||||
#include "aarch64_irq.h"
|
||||
|
||||
extern unsigned int
|
||||
aarch64_init(void);
|
||||
AArch64_init(void);
|
||||
|
||||
extern unsigned int
|
||||
aarch64_get_el(void);
|
||||
AArch64_getEL(void);
|
||||
|
||||
extern unsigned int
|
||||
aarch64_get32r(unsigned long reg);
|
||||
AArch64_getReg32(unsigned long reg);
|
||||
|
||||
extern void
|
||||
aarch64_set32r(unsigned long reg, unsigned int value);
|
||||
AArch64_setReg32(unsigned long reg, unsigned int value);
|
||||
|
||||
extern void
|
||||
aarch64_delay(unsigned long cycles);
|
||||
AArch64_idle(unsigned long cycles);
|
||||
|
||||
extern void
|
||||
aarch64_irq_enable(void);
|
||||
AArch64_enableIRQ(void);
|
||||
|
||||
extern void
|
||||
aarch64_irq_disable(void);
|
||||
AArch64_disableIRQ(void);
|
||||
|
||||
extern void
|
||||
AArch64_memzero(void *addr, unsigned long size);
|
||||
|
||||
#endif /* !AARCH64_H */
|
||||
|
||||
@@ -1,74 +0,0 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (c) 2017-2019 by Löwenware Ltd
|
||||
* Please, refer LICENSE file for legal information
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @file bcm2837.h
|
||||
* @author Ilja Kartašov <ik@lowenware.com>
|
||||
* @brief
|
||||
*
|
||||
* @see https://lowenware.com/
|
||||
*/
|
||||
|
||||
#ifndef BCM2837_H_13CD1DB9_AAD7_4F1C_8669_37DED77135D1
|
||||
#define BCM2837_H_13CD1DB9_AAD7_4F1C_8669_37DED77135D1
|
||||
|
||||
#define PERIPHERAL_BASE 0x3F000000
|
||||
|
||||
/* GPIO */
|
||||
#define GPFSEL1 (PERIPHERAL_BASE + 0x00200004)
|
||||
#define GPSET0 (PERIPHERAL_BASE + 0x0020001C)
|
||||
#define GPCLR0 (PERIPHERAL_BASE + 0x00200028)
|
||||
#define GPPUD (PERIPHERAL_BASE + 0x00200094)
|
||||
#define GPPUDCLK0 (PERIPHERAL_BASE + 0x00200098)
|
||||
|
||||
/* UART MINI */
|
||||
#define AUX_ENABLES (PERIPHERAL_BASE + 0x00215004)
|
||||
#define AUX_MU_IO_REG (PERIPHERAL_BASE + 0x00215040)
|
||||
#define AUX_MU_IER_REG (PERIPHERAL_BASE + 0x00215044)
|
||||
#define AUX_MU_IIR_REG (PERIPHERAL_BASE + 0x00215048)
|
||||
#define AUX_MU_LCR_REG (PERIPHERAL_BASE + 0x0021504C)
|
||||
#define AUX_MU_MCR_REG (PERIPHERAL_BASE + 0x00215050)
|
||||
#define AUX_MU_LSR_REG (PERIPHERAL_BASE + 0x00215054)
|
||||
#define AUX_MU_MSR_REG (PERIPHERAL_BASE + 0x00215058)
|
||||
#define AUX_MU_SCRATCH (PERIPHERAL_BASE + 0x0021505C)
|
||||
#define AUX_MU_CNTL_REG (PERIPHERAL_BASE + 0x00215060)
|
||||
#define AUX_MU_STAT_REG (PERIPHERAL_BASE + 0x00215064)
|
||||
#define AUX_MU_BAUD_REG (PERIPHERAL_BASE + 0x00215068)
|
||||
|
||||
/* IRQ */
|
||||
#define IRQ_BASIC_PENDING (PERIPHERAL_BASE + 0x0000B200)
|
||||
#define IRQ_PENDING_1 (PERIPHERAL_BASE + 0x0000B204)
|
||||
#define IRQ_PENDING_2 (PERIPHERAL_BASE + 0x0000B208)
|
||||
#define FIQ_CONTROL (PERIPHERAL_BASE + 0x0000B20C)
|
||||
#define ENABLE_IRQS_1 (PERIPHERAL_BASE + 0x0000B210)
|
||||
#define ENABLE_IRQS_2 (PERIPHERAL_BASE + 0x0000B214)
|
||||
#define ENABLE_BASIC_IRQS (PERIPHERAL_BASE + 0x0000B218)
|
||||
#define DISABLE_IRQS_1 (PERIPHERAL_BASE + 0x0000B21C)
|
||||
#define DISABLE_IRQS_2 (PERIPHERAL_BASE + 0x0000B220)
|
||||
#define DISABLE_BASIC_IRQS (PERIPHERAL_BASE + 0x0000B224)
|
||||
|
||||
/* SYSTEM TIMER */
|
||||
#define SYSTEM_TIMER_IRQ_0 (1 << 0)
|
||||
#define SYSTEM_TIMER_IRQ_1 (1 << 1)
|
||||
#define SYSTEM_TIMER_IRQ_2 (1 << 2)
|
||||
#define SYSTEM_TIMER_IRQ_3 (1 << 3)
|
||||
|
||||
/* TIMER */
|
||||
#define TIMER_CS (PERIPHERAL_BASE + 0x00003000)
|
||||
#define TIMER_CLO (PERIPHERAL_BASE + 0x00003004)
|
||||
#define TIMER_CHI (PERIPHERAL_BASE + 0x00003008)
|
||||
#define TIMER_C0 (PERIPHERAL_BASE + 0x0000300C)
|
||||
#define TIMER_C1 (PERIPHERAL_BASE + 0x00003010)
|
||||
#define TIMER_C2 (PERIPHERAL_BASE + 0x00003014)
|
||||
#define TIMER_C3 (PERIPHERAL_BASE + 0x00003018)
|
||||
|
||||
#define TIMER_CS_M0 (1 << 0)
|
||||
#define TIMER_CS_M1 (1 << 1)
|
||||
#define TIMER_CS_M2 (1 << 2)
|
||||
#define TIMER_CS_M3 (1 << 3)
|
||||
|
||||
#endif /* !BCM2837_H */
|
||||
Reference in New Issue
Block a user