Update code due to new rules
This commit is contained in:
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/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file bcm2837.h
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#ifndef BCM2837_H_13CD1DB9_AAD7_4F1C_8669_37DED77135D1
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#define BCM2837_H_13CD1DB9_AAD7_4F1C_8669_37DED77135D1
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#define PERIPHERAL_BASE 0x3F000000
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/* Reserve 4 MB for the Kernel and its stack */
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#define MEMORY_LOW (4 * 1024 * 1024)
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#define MEMORY_HIGH PERIPHERAL_BASE
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#define MEMORY_SIZE (MEMORY_HIGH - MEMORY_LOW)
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#define MEMORY_PAGE_SIZE (4 * 1024)
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#define MEMORY_PAGE_COUNT (MEMORY_SIZE / MEMORY_PAGE_SIZE)
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/* GPIO */
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#define GPFSEL1 (PERIPHERAL_BASE + 0x00200004)
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#define GPSET0 (PERIPHERAL_BASE + 0x0020001C)
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#define GPCLR0 (PERIPHERAL_BASE + 0x00200028)
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#define GPPUD (PERIPHERAL_BASE + 0x00200094)
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#define GPPUDCLK0 (PERIPHERAL_BASE + 0x00200098)
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/* UART MINI */
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#define AUX_ENABLES (PERIPHERAL_BASE + 0x00215004)
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#define AUX_MU_IO_REG (PERIPHERAL_BASE + 0x00215040)
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#define AUX_MU_IER_REG (PERIPHERAL_BASE + 0x00215044)
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#define AUX_MU_IIR_REG (PERIPHERAL_BASE + 0x00215048)
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#define AUX_MU_LCR_REG (PERIPHERAL_BASE + 0x0021504C)
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#define AUX_MU_MCR_REG (PERIPHERAL_BASE + 0x00215050)
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#define AUX_MU_LSR_REG (PERIPHERAL_BASE + 0x00215054)
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#define AUX_MU_MSR_REG (PERIPHERAL_BASE + 0x00215058)
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#define AUX_MU_SCRATCH (PERIPHERAL_BASE + 0x0021505C)
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#define AUX_MU_CNTL_REG (PERIPHERAL_BASE + 0x00215060)
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#define AUX_MU_STAT_REG (PERIPHERAL_BASE + 0x00215064)
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#define AUX_MU_BAUD_REG (PERIPHERAL_BASE + 0x00215068)
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/* IRQ */
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#define IRQ_BASIC_PENDING (PERIPHERAL_BASE + 0x0000B200)
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#define IRQ_PENDING_1 (PERIPHERAL_BASE + 0x0000B204)
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#define IRQ_PENDING_2 (PERIPHERAL_BASE + 0x0000B208)
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#define FIQ_CONTROL (PERIPHERAL_BASE + 0x0000B20C)
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#define ENABLE_IRQS_1 (PERIPHERAL_BASE + 0x0000B210)
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#define ENABLE_IRQS_2 (PERIPHERAL_BASE + 0x0000B214)
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#define ENABLE_BASIC_IRQS (PERIPHERAL_BASE + 0x0000B218)
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#define DISABLE_IRQS_1 (PERIPHERAL_BASE + 0x0000B21C)
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#define DISABLE_IRQS_2 (PERIPHERAL_BASE + 0x0000B220)
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#define DISABLE_BASIC_IRQS (PERIPHERAL_BASE + 0x0000B224)
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/* SYSTEM TIMER */
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#define SYSTEM_TIMER_IRQ_0 (1 << 0)
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#define SYSTEM_TIMER_IRQ_1 (1 << 1)
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#define SYSTEM_TIMER_IRQ_2 (1 << 2)
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#define SYSTEM_TIMER_IRQ_3 (1 << 3)
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/* TIMER */
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#define TIMER_CS (PERIPHERAL_BASE + 0x00003000)
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#define TIMER_CLO (PERIPHERAL_BASE + 0x00003004)
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#define TIMER_CHI (PERIPHERAL_BASE + 0x00003008)
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#define TIMER_C0 (PERIPHERAL_BASE + 0x0000300C)
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#define TIMER_C1 (PERIPHERAL_BASE + 0x00003010)
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#define TIMER_C2 (PERIPHERAL_BASE + 0x00003014)
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#define TIMER_C3 (PERIPHERAL_BASE + 0x00003018)
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#define TIMER_CS_M0 (1 << 0)
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#define TIMER_CS_M1 (1 << 1)
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#define TIMER_CS_M2 (1 << 2)
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#define TIMER_CS_M3 (1 << 3)
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#endif /* !BCM2837_H */
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@@ -0,0 +1,41 @@
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/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file timer.c
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#include <aarch64/aarch64.h>
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#include <aarch64/bcm2837.h>
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#include "timer.h"
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#include "log.h"
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const unsigned int m_interval = 200000;
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unsigned int m_current = 0;
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void
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k_timer_init(void)
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{
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m_current = aarch64_get32r(TIMER_CLO);
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m_current += m_interval;
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aarch64_set32r(TIMER_C1, m_current);
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}
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void
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k_timer_irq_handler(void)
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{
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m_current += m_interval;
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aarch64_set32r(TIMER_C1, m_current);
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aarch64_set32r(TIMER_CS, TIMER_CS_M1);
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k_logs("Timer: ");
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k_logu(m_current, 10);
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k_logs("\r\n");
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}
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@@ -0,0 +1,25 @@
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/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file timer.h
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#ifndef TIMER_H_8D327261_47D6_4832_8DC5_31BF1614A21F
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#define TIMER_H_8D327261_47D6_4832_8DC5_31BF1614A21F
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void
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k_timer_init(void);
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void
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k_timer_irq_handler(void);
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#endif /* !TIMER_H */
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@@ -0,0 +1,47 @@
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/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file uart.h
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#ifndef UART_H_8AFC47F9_2953_42C1_A5C1_1AE5A1F52CD0
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#define UART_H_8AFC47F9_2953_42C1_A5C1_1AE5A1F52CD0
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#include "uart_mini.h"
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#include "uart_qemu.h"
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#define UART_MINI 0
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#define UART_QEMU 1
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#ifndef UART_DEFAULT
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#define UART_DEFAULT UART_MINI
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#endif
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#if UART_DEFAULT == UART_MINI
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#define UART_init(...) UARTMini_init(__VA_ARGS__)
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#define UART_get(...) UARTMini_get(__VA_ARGS__)
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#define UART_put(...) UARTMini_put(__VA_ARGS__)
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#elif UART_DEFAULT == UART_QEMU
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#define UART_init(...)
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#define UART_get(...)
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#define UART_put(...) UARTQEMU_put(__VA_ARGS__)
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#else
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#warning "Unsupported UART"
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#endif
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#endif /* !UART_H */
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@@ -0,0 +1,84 @@
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/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file UARTMini.c
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#include <aarch64/aarch64.h>
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#include <aarch64/bcm2837.h>
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#include "UARTMini.h"
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int
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UARTMini_init(void)
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{
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unsigned int sel;
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/* Enable UART Mini and its registers*/
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AArch64_setReg32(AUX_ENABLES, 1);
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/* Disable TX and RX interrupts */
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AArch64_setReg32(AUX_MU_IER_REG, 0);
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/* Disable auto flow control, TX and RX */
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AArch64_setReg32(AUX_MU_CNTL_REG, 0);
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/* Set 8bit mode */
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AArch64_setReg32(AUX_MU_LCR_REG, 3);
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/* Set RTS line HIGH */
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AArch64_setReg32(AUX_MU_MCR_REG, 0);
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/* Set baud rate 115200 */
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AArch64_setReg32(AUX_MU_IER_REG, 0);
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AArch64_setReg32(AUX_MU_IIR_REG, 0xC6);
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AArch64_setReg32(AUX_MU_BAUD_REG, 270);
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sel = AArch64_getReg32(GPFSEL1);
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/* clean and set ALT5 for GPIO14 */
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sel &= ~(7 << 12);
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sel |= (2 << 12);
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/* clean and set ALT5 for GPIO15 */
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sel &= ~(7 << 15);
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sel |= (2 << 15);
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AArch64_setReg32(GPFSEL1, sel);
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AArch64_setReg32(GPPUD, 0);
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AArch64_delay(150);
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AArch64_setReg32(GPPUDCLK0, (1 << 14) | (1 << 15));
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AArch64_delay(150);
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AArch64_setReg32(GPPUDCLK0, 0);
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/* Enable TX and RX */
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AArch64_setReg32(AUX_MU_CNTL_REG, 3);
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return 0;
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}
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int
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UARTMini_put(char c)
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{
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while (1) {
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if (AArch64_getReg32(AUX_MU_LSR_REG) & 0x20)
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break;
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}
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AArch64_setReg32(AUX_MU_IO_REG, c);
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return 0;
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}
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int
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UARTMini_get(char *pc)
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{
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while (1) {
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if (AArch64_getReg32(AUX_MU_LSR_REG) & 0x01)
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break;
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}
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*pc = AArch64_getReg32(AUX_MU_IO_REG) & 0xFF;
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return 0;
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}
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@@ -0,0 +1,28 @@
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/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file UARTMini.h
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#ifndef UART_MINI_H_B0DFA3CF_5B4F_4EB0_B393_391C0069A04F
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#define UART_MINI_H_B0DFA3CF_5B4F_4EB0_B393_391C0069A04F
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int
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UARTMini_init(void);
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int
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UARTMini_put(char c);
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int
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UARTMini_get(char *pc);
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#endif /* !UART_MINI_H */
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@@ -0,0 +1,28 @@
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/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file uart.c
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#include "uart_qemu.h"
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#define UARTQEMU_BASE 0x09000000;
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volatile unsigned int *UART0 = (unsigned int *)UARTQEMU_BASE;
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int
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UARTQEMU_put(unsigned char c)
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{
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*UART0 = (unsigned int) c;
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return 0;
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}
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@@ -0,0 +1,22 @@
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/******************************************************************************
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*
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* Copyright (c) 2017-2019 by Löwenware Ltd
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* Please, refer LICENSE file for legal information
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*
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******************************************************************************/
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/**
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* @file uart_qemu.h
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* @author Ilja Kartašov <ik@lowenware.com>
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* @brief
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*
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* @see https://lowenware.com/
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*/
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#ifndef UART_QEMU_H_EDB39A0E_9BED_4A47_91CD_E804A9B4E8ED
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#define UART_QEMU_H_EDB39A0E_9BED_4A47_91CD_E804A9B4E8ED
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int
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UARTQEMU_put(unsigned char c);
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#endif /* !UART_QEMU_H */
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